Currently available parasitic antenna arrays may implement variable reactance via a single component, such as a PIN diode, a varactor diode, or a variable capacitor. Further, with said currently available parasitic antenna array implementations, a standard DC bias network may be attached which uses a large resistance or inductance for an RF choke. In these currently available implementations, the effects of the interconnect impedance (such as via inductance) are neglected. Such effects may become increasingly significant at higher frequencies, especially if tuned structures, such as quarter wavelength lines, are used. Thus, these currently available implementations fail to produce the requisite impedances for proper high efficiency operation of a parasitic array at higher microwave frequencies (ex. —frequencies greater than 3 Gigahertz (GHz)).
Thus, it would be desirable to provide a parasitic antenna array implementation which obviates the problems associated with currently available implementations.